EP2C8T144I8N Datasheet, PDF (364/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Active Serial Configuration (Serial Configuration Devices)
configuration device. The configuration device then provides data on its
serial data output (DATA) pin, which connects to the DATA0 input of the
Cyclone II device.
After the Cyclone II device receives all the configuration bits, it releases
the open-drain CONF_DONE pin, which is then pulled high by an external
10-kΩ resistor. Also, the Cyclone II device stops driving the DCLK signal.
Initialization begins only after the CONF_DONE signal reaches a logic high
level. The CONF_DONE pin must have an external 10-kΩ pull-up resistor
in order for the device to initialize. All AS configuration pins (DATA0,
DCLK, nCSO, and ASDO) have weak internal pull-up resistors which are
always active. After configuration, these pins are set as input tri-stated
and are pulled high by the internal weak pull-up resistors.
Initialization Stage
In Cyclone II devices, the initialization clock source is either the
Cyclone II 10-MHz (typical) internal oscillator (separate from the AS
internal oscillator) or the optional CLKUSR pin. The internal oscillator is
the default clock source for initialization. If the internal oscillator is used,
the Cyclone II device provides itself with enough clock cycles for proper
initialization. The advantage of using the internal oscillator is you do not
need to send additional clock cycles from an external source to the
CLKUSR pin during the initialization stage. Additionally, you can use the
CLKUSR pin as a user I/O pin.
If you want to delay the initialization of the device, you can use the
CLKUSR pin option. Using the CLKUSR pin allows you to control when
your device enters user mode. The device can be delayed from entering
user mode for an indefinite amount of time. When you enable the User
Supplied Start-Up Clock option, the CLKUSR pin is the initialization
clock source. Supplying a clock on CLKUSR does not affect the
configuration process. After all configuration data has been accepted and
CONF_DONE goes high, Cyclone II devices require 299 clock cycles to
initialize properly and support a CLKUSR f_MAX of 100 MHz.
13–10
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007