EP2C8T144I8N Datasheet, PDF (434/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Operation Control
When the TAP controller is in the TEST_LOGIC/RESET state, the BST
circuitry is disabled, the device is in normal operation, and the instruction
register is initialized with IDCODE as the initial instruction. At device
power-up, the TAP controller starts in this TEST_LOGIC/RESET state. In
addition, forcing the TAP controller to the TEST_LOGIC/RESET state is
done by holding TMS high for five TCK clock cycles. Once in the
TEST_LOGIC/RESET state, the TAP controller remains in this state as
long as TMS is held high (while TCK is clocked). Figure 14–6 shows the
timing requirements for the IEEE Std. 1149.1 signals.
Figure 14–6. IEEE Std. 1149.1 Timing Waveforms
TMS
TDI
TCK
TDO
Signal
to be
Captured
Signal
to be
Driven
t_JCH
t_JCP
t_JCL
t_JPSU
t_JPZX
t_JSSU
t_JSZX
t_JPCO
t_JSH
t_JSCO
t_JPH
t_JPXZ
t_JSXZ
To start IEEE Std. 1149.1 operation, select an instruction mode by
advancing the TAP controller to the shift instruction register (SHIFT_IR)
state and shift in the appropriate instruction code on the TDI pin. The
waveform diagram in Figure 14–7 represents the entry of the instruction
code into the instruction register. It shows the values of TCK, TMS, TDI,
TDO, and the states of the TAP controller. From the RESET state, TMS is
clocked with the pattern 01100 to advance the TAP controller to
SHIFT_IR.
14–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007