EP2C8T144I8N Datasheet, PDF (209/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Table 7–9. Clock Control Block Inputs (Part 2 of 2)
Input
PLL outputs
Internal logic
Description
The PLL counter outputs can drive the global
clock network.
The global clock network can also be driven
through the logic array routing to enable
internal logic (LEs) to drive a high fan-out, low
skew signal path.
In Cyclone II devices, the dedicated clock input pins, PLL counter
outputs, dual-purpose clock I/O inputs, and internal logic can all feed the
clock control block for each global clock network. The output from the
clock control block in turn feeds the corresponding global clock network.
The clock control blocks are arranged on the device periphery and there
are a maximum of 16 clock control blocks available per Cyclone II device.
The control block has two functions:
■ Dynamic global clock network clock source selection
■ Global clock network power-down (dynamic enable and disable)
Figure 7–11 shows the clock control block.
Altera Corporation
February 2007
7–25
Cyclone II Device Handbook, Volume 1