EP2C8T144I8N Datasheet, PDF (223/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

8. Cyclone II Memory Blocks
CII51008-2.4
Introduction
Overview
Altera Corporation
February 2008
Cyclone^® II devices feature embedded memory structures to address the
on-chip memory needs of FPGA designs. The embedded memory
structure consists of columns of M4K memory blocks that can be
configured to provide various memory functions such as RAM, first-in
first-out (FIFO) buffers, and ROM. M4K memory blocks provide over
1 Mbit of RAM at up to 250-MHz operation (see Table 8–2 on page 8–2 for
total RAM bits per density).
The M4K blocks support the following features:
■ Over 1 Mbit of RAM available without reducing available logic
■ 4,096 memory bits per block (4,608 bits per block including parity)
■ Variable port configurations
■ True dual-port (one read and one write, two reads, or two writes)
operation
■ Byte enables for data input masking during writes
■ Initialization file to pre-load content of memory in RAM and ROM
modes
■ Up to 250-MHz operation
Table 8–1 summarizes the features supported by the M4K memory.
Table 8–1. Summary of M4K Memory Features (Part 1 of 2)
Feature
Maximum performance (1)
Total RAM bits (including parity bits)
Configurations
Parity bits
Byte enable
M4K Blocks
250 MHz
4,608
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
v
v
8–1