EP2C8T144I8N Datasheet, PDF (108/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Operating Conditions
Table 5–3. DC Characteristics for User I/O, Dual-Purpose, and Dedicated Pins (Part 2 of 2)
Symbol
Parameter
Conditions
R_CONF (5) (6)
Value of I/O pin
pull-up resistor
before and during
configuration
V_IN = 0 V; V_CCIO = 3.3 V
V_IN = 0 V; V_CCIO = 2.5 V
V_IN = 0 V; V_CCIO = 1.8 V
V_IN = 0 V; V_CCIO = 1.5 V
V_IN = 0 V; V_CCIO = 1.2 V
Recommended
(7)
value of I/O pin
external pull-down
resistor before and
during configuration
Minimum Typical Maximum Unit
10
25
50
kΩ
15
35
70
kΩ
30
50
100
kΩ
40
75
150
kΩ
50
90
170
kΩ
—
1
2
kΩ
Notes to Table 5–3:
(1) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V_CCINT and V_CCIO are
powered.
(2) The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to the
voltages shown in Table 5–4, based on input duty cycle for input currents less than 100 mA. The overshoot is
dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle.
(3) This value is specified for normal device operation. The value may vary during power-up. This applies for all V_CCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(4) Maximum values depend on the actual T_J and design utilization. See the Excel-based PowerPlay Early Power
Estimator (www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum values. Refer to
“Power Consumption” on page 5–13 for more information.
(5) R_CONF values are based on characterization. R_CONF = V_CCIO/I_RCONF. R_CONF values may be different if V_IN value is
not 0 V. Pin pull-up resistance values will be lower if an external source drives the pin higher than V_CCIO.
(6) Minimum condition at –40°C and high V_CC, typical condition at 25°C and nominal V_CC and maximum condition at
125°C and low V_CC for R_CONF values.
(7) These values apply to all V_CCIO settings.
Table 5–4 shows the maximum V_IN overshoot voltage and the
dependency on the duty cycle of the input signal. Refer to Table 5–3 for
more information.
Table 5–4. V_IN Overshoot Voltage for All Input Buffers
Maximum V_IN (V)
4.0
4.1
4.2
4.3
4.4
4.5
Input Signal Duty Cycle
100% (DC)
90%
50%
30%
17%
10%
5–4
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008