EP2C8T144I8N Datasheet, PDF (239/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
Independent Clock Mode
Cyclone II memory blocks can implement independent clock mode for
true dual-port memory. In this mode, a separate clock is available for each
port (A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port also supports
independent clock enables for port A and B registers. However, ports do
not support asynchronous clear signals for the registers.
Figure 8–13 shows a memory block in independent clock mode.
Altera Corporation
February 2008
8–17
Cyclone II Device Handbook, Volume 1