EP2C8T144I8N Datasheet, PDF (186/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II PLL Hardware Overview
Table 7–2 provides an overview of the Cyclone II PLL features.
Table 7–2. Cyclone II PLL Features
Feature
Description
Clock multiplication and division
m / (n × post-scale counter) (1)
Phase shift
Down to 125-ps increments (2), (3)
Programmable duty cycle
v
Number of internal clock outputs
Up to three per PLL (4)
Number of external clock outputs
One per PLL (4)
Locked port can feed logic array
v
PLL clock outputs can feed logic array
v
Manual clock switchover
v
Gated lock
v
Notes to Table 7–2:
(1) m and post-scale counter values range from 1 to 32. n ranges from 1 to 4.
(2) The smallest phase shift is determined by the voltage control oscillator (VCO)
period divided by 8.
(3) For degree increments, Cyclone II devices can shift output frequencies in
increments of at least 45°. Smaller degree increments are possible depending on
the VCO frequency.
(4) The Cyclone II PLL has three output counters that drive the global clock network.
One of these output counters (c2) can also drive a dedicated external I/O pin
(single ended or differential). This counter output can also drive the external clock
output (PLL<#>_OUT) and internal global clock network at the same time.
Cyclone II PLL
Hardware
Overview
Cyclone II devices contain up to four PLLs that are arranged in the four
corners of the Cyclone II device as shown in Figure 7–1, which shows a
top-level diagram of the Cyclone II device and the PLL locations.
7–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007