EP2C8T144I8N Datasheet, PDF (226/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Overview
Figure 8–1. M4K Control Signal Selection
Dedicated
6
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clock_b
clocken_b
renwe_b
aclr_b
addressstall_b
byteena_b
clock_a
clocken_a
renwe_a
aclr_a
addressstall_a
byteena_a
f
Parity Bit Support
Error detection using parity check is possible using the parity bit, with
additional logic implemented in LEs to ensure data integrity. Parity-size
data words can also be used for other purposes such as storing
user-specified control bits.
Refer to the Using Parity to Detect Errors White Paper for more
information.
Byte Enable Support
All M4K memory blocks support byte enables that mask the input data so
that only specific bytes of data are written. The unwritten bytes retain the
previous written value. The write enable (wren) signals, along with the
byte enable (byteena) signals, control the RAM block’s write operations.
The default value for the byte enable signals is high (enabled), in which
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Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008