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EP2C5T144I8N Datasheet, PDF (7/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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Contents
Phase Lock Loop (PLL) .................................................................................................................. 9â15
Clock Delay Control ....................................................................................................................... 9â15
DQS Postamble ............................................................................................................................... 9â16
DDR Input Registers ...................................................................................................................... 9â18
DDR Output Registers ................................................................................................................... 9â21
Bidirectional DDR Registers ......................................................................................................... 9â22
Conclusion ............................................................................................................................................ 9â24
Document Revision History ............................................................................................................... 9â25
Section IV. I/O Standards
Revision History .................................................................................................................................... 9â1
Chapter 10. Selectable I/O Standards in Cyclone II Devices
Introduction .......................................................................................................................................... 10â1
Supported I/O Standards ................................................................................................................... 10â1
3.3-V LVTTL (EIA/JEDEC Standard JESD8-B) .......................................................................... 10â3
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B) ..................................................................... 10â4
3.3-V (PCI Special Interest Group [SIG] PCI Local Bus Specification Revision 3.0) ............. 10â4
3.3-V PCI-X ...................................................................................................................................... 10â6
Easy-to-Use, Low-Cost PCI Express Solution ............................................................................ 10â6
2.5-V LVTTL (EIA/JEDEC Standard EIA/JESD8-5) ................................................................. 10â7
2.5-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-5) ............................................................ 10â7
SSTL-2 Class I and II (EIA/JEDEC Standard JESD8-9A) ......................................................... 10â7
Pseudo-Differential SSTL-2 ........................................................................................................... 10â8
1.8-V LVTTL (EIA/JEDEC Standard EIA/JESD8-7) ................................................................. 10â9
1.8-V LVCMOS (EIA/JEDEC Standard EIA/JESD8-7) .......................................................... 10â10
SSTL-18 Class I and II .................................................................................................................. 10â10
1.8-V HSTL Class I and II ............................................................................................................ 10â11
Pseudo-Differential SSTL-18 Class I and Differential SSTL-18 Class II ............................... 10â12
1.8-V Pseudo-Differential HSTL Class I and II ........................................................................ 10â13
1.5-V LVCMOS (EIA/JEDEC Standard JESD8-11) .................................................................. 10â14
1.5-V HSTL Class I and II ............................................................................................................ 10â14
1.5-V Pseudo-Differential HSTL Class I and II ........................................................................ 10â15
LVDS, RSDS and mini-LVDS ..................................................................................................... 10â16
Differential LVPECL .................................................................................................................... 10â17
Cyclone II I/O Banks ........................................................................................................................ 10â18
Programmable Current Drive Strength .......................................................................................... 10â24
Voltage-Referenced I/O Standard Termination ...................................................................... 10â26
Differential I/O Standard Termination .................................................................................... 10â26
I/O Driver Impedance Matching (RS) and Series Termination (RS) ..................................... 10â27
Pad Placement and DC Guidelines ................................................................................................. 10â27
Differential Pad Placement Guidelines ..................................................................................... 10â28
VREF Pad Placement Guidelines ................................................................................................. 10â29
DC Guidelines ............................................................................................................................... 10â32
5.0-V Device Compatibility .............................................................................................................. 10â34
Altera Corporation
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Cyclone II Device Handbook, Volume 1
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