EP2C5T144I8N Datasheet, PDF (135/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins Notes (1), (2) (Part 2 of 2)
Parameter
Paths
Affected
Number
of
Settings
Fast Corner (3)
Min Max
Offset Offset
–6 Speed
Grade
Min Max
Offset Offset
–7 Speed
Grade (4)
Min Max
Offset Offset
–8 Speed Grade
Unit
Min Max
Offset Offset
Input Delay Pad ->
8
from Pin to I/O input
Input
register
Register
0
2669
0
4482
0
4834
0
4859 ps
0 2802 —
—
0 4671 —
— ps
Delay from I/O
2
Output
output
Register to register -
Output Pin > Pad
0
308
0
572
0
648
0
682 ps
0
324
—
—
0
626
—
— ps
Notes to Table 5–37 :
(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
(2) The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
(3) The value in the first row represents the fast corner timing parameter for industrial and automotive devices. The
second row represents the fast corner timing parameter for commercial devices.
(4) The value in the first row is for automotive devices. The second row is for commercial devices.
Default Capacitive Loading of Different I/O Standards
Refer to Table 5–38 for default capacitive loading of different I/O
standards.
Table 5–38. Default Loading of Different I/O Standards for Cyclone II Device
(Part 1 of 2)
I/O Standard
LVTTL
LVCMOS
2.5V
1.8V
1.5V
PCI
PCI-X
SSTL_2_CLASS_I
SSTL_2_CLASS_II
SSTL_18_CLASS_I
Capacitive Load
Unit
0
pF
0
pF
0
pF
0
pF
0
pF
10
pF
10
pF
0
pF
0
pF
0
pF
Altera Corporation
February 2008
5–31
Cyclone II Device Handbook, Volume 1