EP2C5T144I8N Datasheet, PDF (420/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Device Configuration Pins
Table 13–11. Dedicated Configuration Pins on the Cyclone II Device (Part 3 of 5)
Pin Name
CONF_DONE
User Configuration
Mode Scheme
Pin Type
N/A All
Bidirectional
open-drain
Description
This pin is a status output and input.
The target Cyclone II device drives the CONF_DONE
pin low before and during configuration. Once the
Cyclone II device receives all the configuration data
without error and the initialization cycle starts, it
releases CONF_DONE. Driving CONF_DONE low
during user mode does not affect the configured
device. Do not drive CONF_DONE low before the
device enters user mode.
After the Cyclone II device receives all the data, the
CONF_DONE pin transitions high, and the device
initializes and enters user mode. The CONF_DONE
pin must have an external 10-kΩ pull-up resistor in
order for the device to initialize.
Driving CONF_DONE low after configuration and
initialization does not affect the configured device.
The enhanced configuration devices’ and EPC2
devices’ OE and nCS pins are connected to the
Cyclone II device’s nSTATUS and CONF_DONE pins,
respectively, and have optional internal
programmable pull-up resistors. If internal pull-up
resistors on the enhanced configuration device are
used, external 10-kΩ pull-up resistors should not be
used on these pins. When using EPC2 devices, you
should only use external 10-kΩ pull-up resistors.
nCE
N/A All
Input
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
This pin is an active-low chip enable. The nCE pin
activates the device with a low signal to allow
configuration. The nCE pin must be held low during
configuration, initialization, and user mode. In single
device configuration, it should be tied low. In multiple
device configuration, nCE of the first device is tied low
while its nCEO pin is connected to nCE of the next
device in the chain.
The nCE pin must also be held low for successful
JTAG programming of the FPGA.
The input buffer on this pin supports hysteresis using
Schmitt trigger circuitry.
13–66
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007