EP2C5T144I8N Datasheet, PDF (257/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
You can use any of the user I/O pins for commands and addresses.
Because of the symmetrical setup and hold time for the command and
address pins at the memory device, you may need to generate these
signals from the negative edge of the system clock.
The clocks to the SDRAM device are called CK and CK#. Use any of the
user I/O pins via the DDR registers to generate the CK and CK# signals
to meet the t_DQSS requirements of the DDR SDRAM or DDR2 SDRAM
device. The memory device’s t_DQSS requires the positive edge of the write
DQS signal to be within 25% of the positive edge of the DDR SDRAM and
DDR2 SDRAM clock input. Because of strict skew requirements between
CK and CK# signals, use adjacent pins to generate the clock pair.
Surround the pair with buffer pins tied to V_CC and pins tied to ground for
better noise immunity from other signals.
Read & Write Operation
When reading from the memory, DDR and DDR2 SDRAM devices send
the data edge-aligned relative to the data strobe. To properly read the
data, the data strobe must be center-aligned relative to the data inside the
FPGA. Cyclone II devices feature clock delay control circuitry to shift the
data strobe to the middle of the data window. Figure 9–1 shows an
example of how the memory sends out the data and data strobe for a
burst-of-two operation.
Altera Corporation
February 2007
9–3
Cyclone II Device Handbook, Volume 1