EP2C5T144I8N Datasheet, PDF (294/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Supported I/O Standards
Pseudo-Differential SSTL-18 Class I and Differential SSTL-18
Class II
The 1.8-V differential SSTL-18 standard is formulated under JEDEC
Standard, JESD8-15: Stub Series Terminated Logic for 1.8V (SSTL-18).
The differential SSTL-18 I/O standard is a 1.8-V standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
supports differential signals in systems using the SSTL-18 standard and
supplements the SSTL-18 standard for differential clocks. Refer to
Figures 10–9 and 10–10 for details on differential SSTL-18 termination.
Cyclone II devices do not support true differential SSTL-18 standards.
Cyclone II devices support pseudo-differential SSTL-18 outputs for
PLL_OUT pins and pseudo-differential SSTL-18 inputs for clock pins.
Pseudo-differential inputs require an input reference voltage as opposed
to the true differential inputs. Refer to Table 10–1 on page 10–2 for
information about pseudo-differential SSTL.
Figure 10–9. Differential SSTL-18 Class I Termination
VTT = 0.9 V
VTT = 0.9 V
Differential
Transmitter
25 Ω
50 Ω
Z0 = 50 Ω
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
10–12
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008