EP2C5T144I8N Datasheet, PDF (356/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Configuration Overview
Table 13–1. Cyclone II Configuration Schemes
Configuration Scheme
AS (20 MHz)
PS
Fast AS (40 MHz) (1)
JTAG-based Configuration (2)
MSEL1
0
0
1
(3)
MSEL0
0
1
0
(3)
Notes to Table 13–1:
(1) Only the EPCS16 and EPCS64 devices support a DCLK up to 40 MHz clock; other
EPCS devices support a DCLK up to 20 MHz. Refer to the Serial Configuration
Devices Data Sheet for more information.
(2) JTAG-based configuration takes precedence over other configuration schemes,
which means MSEL pin settings are ignored.
(3) Do not leave the MSEL pins floating; connect them to V_CCIO or ground. These pins
support the non-JTAG configuration scheme used in production. If you are only
using JTAG configuration, you should connect the MSEL pins to ground.
You can download configuration data to Cyclone II FPGAs with the AS,
PS, or JTAG interfaces using the options in Table 13–2.
Table 13–2. Cyclone II Device Configuration Schemes
Configuration Scheme
AS configuration
PS configuration
JTAG-based configuration
Description
Configuration using serial configuration
devices (EPCS1, EPCS4, EPCS16 or
EPCS64 devices)
Configuration using enhanced configuration
devices (EPC4, EPC8, and EPC16 devices),
EPC2 and EPC1 configuration devices, an
intelligent host (microprocessor), or a
download cable
Configuration via JTAG pins using a
download cable, an intelligent host
(microprocessor), or the Jam™ Standard
Test and Programming Language (STAPL)
13–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007