EP2C5T144I8N Datasheet, PDF (176/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Duty Cycle Distortion
Table 5–57. Maximum for DDIO Output on Row Pins with PLL in the Clock
Path Notes (1), (2) (Part 2 of 2)
Row Pins with PLL in the Clock Path C6
C7
C8 Unit
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
HSTL-18 Class I
HSTL-15 Class I
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
280
280
280
ps
150
190
230
ps
155
200
230
ps
180
240
260
ps
180
235
235
ps
205
220
220
ps
150
190
230
ps
155
200
230
ps
180
240
260
ps
Differential HSTL-18 Class I
Differential HSTL-15 Class I
LVDS
Simple RSDS
Mini LVDS
PCI
PCI-X
180
235
235
ps
205
220
220
ps
95
110
120
ps
100
155
155
ps
95
110
120
ps
285
305
335
ps
285
305
335
ps
Notes to Table 5–57:
(1) The DCD specification is characterized using the maximum drive strength
available for each I/O standard.
(2) Numbers are applicable for commercial, industrial, and automotive devices.
For DDIO outputs, you can calculate actual half period from the
following equation:
Actual half period = ideal half period – maximum DCD
For example, if the DDR output I/O standard is SSTL-2 Class II, the
maximum DCD for a –5 device is 155 ps (refer to Table 5–57). If the clock
frequency is 167 MHz, the half-clock period T/2 is:
T/2 = 1/(2* f )= 1 /(2*167 MHz) = 3 ns = 3000 ps
5–72
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008