EP2C5T144I8N Datasheet, PDF (303/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Altera Corporation
February 2008
Selectable I/O Standards in Cyclone II Devices
Additionally, each Cyclone II I/O bank has its own VCCIO pins. Any
single I/O bank can only support one V_CCIO setting from among 1.5, 1.8,
2.5 or 3.3 V. Although there can only be one V_CCIO voltage per I/O bank,
Cyclone II devices permit additional input signaling capabilities, as
shown in Table 10–4.
Table 10–4. Acceptable Input Levels for LVTTL and LVCMOS
Bank V_CCIO (V)
3.3
2.5
1.8
1.5
3.3
v
v
v (2)
v (2)
Acceptable Input Levels (V)
2.5
1.8
v (1)
v
v (2)
v
v (2)
v
1.5
v (1)
v
Notes to Table 10–4:
(1) Because the input level does not drive to the rail, the input buffer does not
completely shut off, and the I/O current is slightly higher than the default value.
(2) These input values overdrive the input buffer, so the pin leakage current is
slightly higher than the default value. To drive inputs higher than V_CCIO but less
than 4.0 V, disable the PCI clamping diode and turn on Allow voltage overdrive
for LVTTL/LVCMOS input pins in Settings > Device > Device and Pin Options
> Pin Placement tab. This setting allows input pins with LVTTL or LVCMOS I/O
standards to be placed by the Quartus II software in an I/O bank with a lower
V_CCIO voltage than the voltage specified by the pins.
Any number of supported single-ended or differential standards can be
simultaneously supported in a single I/O bank as long as they use
compatible V_CCIO levels for input and output pins. For example, an I/O
bank with a 2.5-V V_CCIO setting can support 2.5-V LVTTL inputs and
outputs, 2.5-V LVDS-compatible inputs and outputs, and 3.3-V LVCMOS
inputs only.
Voltage-referenced standards can be supported in an I/O bank using any
number of single-ended or differential standards as long as they use the
same V_REF and a compatible V_CCIO value. For example, if you choose to
implement both SSTL-2 and SSTL-18 in your Cyclone II device, I/O pins
using these standards—because they require different V_REF values—must
be in different banks from each other. However, the same I/O bank can
support SSTL-2 and 2.5-V LVCMOS with the V_CCIO set to 2.5 V and the
V_REF set to 1.25 V.
Refer to “Pad Placement and DC Guidelines” on page 10–27 for more
information.
10–21
Cyclone II Device Handbook, Volume 1