EP2C5T144I8N Datasheet, PDF (229/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
Figure 8–3 shows an address clock enable block diagram. The address
register output is fed back to its input via a multiplexer. The multiplexer
output is selected by the address clock enable (addressstall) signal.
Address latching is enabled when the addressstall signal goes high
(active high). The output of the address register is then continuously fed
into the input of the register until the addressstall signal goes low.
Figure 8–3. Cyclone II Address Clock Enable Block Diagram
address[0]
1
address[0]
0
register
address[0]
address[N]
addressstall
clock
1
address[N]
0
register
address[N]
The address clock enable is typically used for cache memory applications
to improve efficiency during a cache-miss. The default value for the
address clock enable signals is low (disabled). Figures 8–4 and 8–5 show
the address clock enable waveforms during the read and write cycles,
respectively.
Altera Corporation
February 2008
8–7
Cyclone II Device Handbook, Volume 1