EP2C5T144I8N Datasheet, PDF (238/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Clock Modes
ROM Mode
Cyclone II memory blocks support ROM mode. A MIF initializes the
ROM contents of these blocks. The address lines of the ROM are
registered. The outputs can be registered or unregistered. The ROM read
operation is identical to the read operation in the single-port RAM
configuration.
f
FIFO Buffer Mode
A single clock or dual clock FIFO buffer may be implemented in the
memory blocks. Dual clock FIFO buffers are useful when transferring
data from one clock domain to another clock domain. All FIFO memory
configurations have synchronous inputs. However, the FIFO buffer
outputs are always combinational (i.e., not registered). Simultaneous read
and write from an empty FIFO buffer is not supported.
For more information on FIFO buffers, refer to the Single- & Dual-Clock
FIFO Megafunctions User Guide.
Clock Modes
Depending on which memory mode is selected, the following clock
modes are available:
■ Independent
■ Input/output
■ Read/write
■ Single-clock
Table 8–7 shows these clock modes supported by all memory blocks
when configured in each respective memory modes.
Table 8–7. Cyclone II Memory Clock Modes
Clocking Modes
Independent
Input/output
Read/write
Single clock
True Dual-Port
Mode
v
v
v
Simple Dual-Port
Mode
v
v
v
Single-Port
Mode
v
v
8–16
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008