EP2C5T144I8N Datasheet, PDF (260/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interface Standards
QDRII SRAM devices use the following clock signals:
■ Input clocks K and K#
■ Optional output clocks C and C#
■ Echo clocks CQ and CQn
Clocks C#, K#, and CQn are logical complements of clocks C, K, and CQ,
respectively. Clocks C, C#, K, and K# are inputs to the QDRII SRAM, and
clocks CQ and CQn are outputs from the QDRII SRAM. Cyclone II
devices use single-clock mode for QDRII SRAM interfacing. The K and
K# clocks are used for both read and write operations, and the C and C#
clocks are unused.
You can generate C, C#, K, and K# clocks using any of the I/O registers
via the DDR registers. Due to strict skew requirements between K and K#
signals, use adjacent pins to generate the clock pair. Surround the pair
with buffer pins tied to V_CC and pins tied to ground for better noise
immunity from other signals.
In Cyclone II devices, another DQS pin implements the CQn pin in the
QDRII SRAM memory interface. These pins are denoted by DQS/CQ# in
the pin table. Connect CQ and CQn pins to the Cyclone II DQS/CQ and
DQS/CQ# pins of the same DQ groups, respectively. You must configure
the DQS/CQ and DQS/CQ# as bidirectional pins. However, because CQ
and CQn pins are output-only pins from the memory device, the
Cyclone II device’s QDRII SRAM memory interface requires that you
ground the DQS/CQ and DQS/CQ# output enable. To capture data
presented by the memory device, connect the shifted CQ signal to register
C_I and input register A_I. Connect the shifted CQn to input register B_I.
Figure 9–4 shows the CQ and CQn connections for a QDRII SRAM read.
9–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007