EP2C5T144I8N Datasheet, PDF (300/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II I/O Banks
Figure 10–18. LVPECL AC Coupled Termination
Output Buffer
10 to 100 nF
Z = 50 Ω
V_CCIO
V_CCIO
R1
R1
100 Ω
10 to 100 nF _{Z = 50 Ω}
R2
R2
Input Buffer
Cyclone II I/O
Banks
The I/O pins on Cyclone II devices are grouped together into I/O banks,
and each bank has a separate power bus. This allows you to select the
preferred I/O standard for a given bank, enabling tremendous flexibility
in the Cyclone II device’s I/O support.
EP2C5 and EP2C8 devices support four I/O banks. EP2C15, EP2C20,
EP2C35, EP2C50, and EP2C70 devices support eight I/O banks. Each
device I/O pin is associated with one of these specific, numbered I/O
banks (refer to Figures 10–19 and 10–20). To accommodate
voltage-referenced I/O standards, each Cyclone II I/O bank has separate
V_REF bus. Each bank in EP2C5, EP2C8, EP2C15, EP2C20, EP2C35, and
EP2C50 devices supports two VREF pins and each bank in EP2C70
devices supports four VREF pins. In the event these pins are not used as
VREF pins, they may be used as regular I/O pins. However, they are
expected to have slightly higher pin capacitance than other user I/O pins
when used with regular user I/O pins.
10–18
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008