EP2C5T144I8N Datasheet, PDF (295/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Selectable I/O Standards in Cyclone II Devices
Figure 10–10. Differential SSTL-18 Class II Termination
VTT = 0.9 V VTT = 0.9 V
VTT = 0.9 V VTT = 0.9 V
Differential
Transmitter
50 Ω
25 Ω
50 Ω
50 Ω
Z0 = 50 Ω
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
1.8-V Pseudo-Differential HSTL Class I and II
The 1.8-V differential HSTL specification is the same as the 1.8-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0 to 1.8-V HSTL logic switching range such as QDR
memory clock interfaces. Cyclone II devices support both input and
output levels. Refer to Figures 10–11 and 10–12 for details on 1.8-V
differential HSTL termination.
Cyclone II devices do not support true 1.8-V differential HSTL standards.
Cyclone II devices support pseudo-differential HSTL outputs for
PLL_OUT pins and pseudo-differential HSTL inputs for clock pins.
Pseudo-differential inputs require an input reference voltage as opposed
to the true differential inputs. Refer to Table 10–1 on page 10–2 for
information about pseudo-differential HSTL.
Figure 10–11. 1.8-V Differential HSTL Class I Termination
V_TT = 0.9 V
V_TT = 0.9 V
Differential
Transmitter
50 Ω
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
Altera Corporation
February 2008
10–13
Cyclone II Device Handbook, Volume 1