EP2C5T144I8N Datasheet, PDF (264/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

DDR Memory Interface Pins
DDR Memory
Interface Pins
Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to
interface with external memory. Figure 9–6 shows the DQ and DQS pins
in the ×8/×9 mode.
Figure 9–6. Cyclone II Device DQ & DQS Groups in ×8/×9 Mode Notes (1), (3)
DQ Pins
DQS Pin (2)
DQ Pins
DM Pin
Notes to Figure 9–6:
(1) Each DQ group consists of a DQS pin, a DM pin, and up to nine DQ pins.
(2) For the QDRII memory interface, other DQS pins implement the CQn pins. These pins are denoted by DQS/CQ# in
the pin table.
(3) This is an idealized pin layout. For the actual pin layout, refer to the pin tables in the PCB Layout Guidelines section
of the Cyclone II Device Handbook, Volume 1.
Data & Data Strobe Pins
Cyclone II data pins for the DDR memory interfaces are called DQ pins.
Cyclone II devices can use either bidirectional data strobes or
unidirectional read clocks. Depending on the external memory interface,
either the memory device’s read data strobes or read clocks feed the DQS
pins.
In Cyclone II devices, all the I/O banks support DDR and DDR2 SDRAM
and QDRII SRAM memory at up to 167 MHz. All the I/O banks support
DQS signals with the DQ bus modes of ×8/×9 and ×16/×18. Cyclone II
devices can support either bidirectional data strobes or unidirectional
read clocks.
1 DDR2 and QDRII interfaces with class II I/O standard can only
be implemented on the top and bottom I/O banks of the
Cyclone II device.
9–10
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007