EP2C5T144I8N Datasheet, PDF (267/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
directly to the clock control block. For the larger Cyclone II devices, the
corner DQS signals are multiplexed before they are routed to the clock
control block. When you use the corner DQS pins for DDR
implementation, there is a degradation in the performance of the memory
interface. The clock control block is used to select from a number of input
clock sources, in this case either PLL clock outputs or DQS pins, to drive
onto the global clock bus. Figure 9–7 shows the corner DQS signal
mappings for EP2C15 through EP2C70 devices.
Figure 9–7. Corner DQS Signal Mapping for EP2C15–EP2C70 Devices
DQS2L
DQS0L
DQS1L
DQS3L
DQS1T
PLL 3
3
(4)
DQS[5..2]T
4
DQS0T
PLL 2
(4)
(3)
4
Global Clock
Bus (2)
4
Clock Control
Block (1)
(3)
3
4
3
Clock Control
Block (1)
4
(3)
PLL 1
(4)
DQS1B
4
DQS[5..2]B
(3)
3
PLL 4
(4)
DQS0B
DQS2R
DQS0R
DQS1R
DQS3R
Notes to Figure 9–7:
(1) There are four control blocks on each side.
(2) There are a total of 16 global clocks available.
(3) Only one of the corner DQS pins in each corner can feed the clock control block at a time. The other DQS pins can
be used as general purpose I/O pins.
(4) PLL resource can be lost if all DQS pins from one side are used at the same time.
(5) Top/bottom and side IOE have different timing.
Altera Corporation
February 2007
9–13
Cyclone II Device Handbook, Volume 1