EP2C5T144I8N Datasheet, PDF (346/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Architecture
f
See the Cyclone II Memory Blocks chapter in Volume 1 of the Cyclone II
Device Handbook for more information on Cyclone II M4K memory
blocks.
Refer to AN 306: Techniques for Implementing Multipliers in FPGA Devices
for more information on soft multipliers.
Architecture
Each embedded multiplier consists of the following elements:
■ Multiplier stage
■ Input and output registers
■ Input and output interfaces
Figure 12–2 shows the multiplier block architecture.
Figure 12–2. Multiplier Block Architecture
signa (1)
signb (1)
aclr
clock
ena
Data A
Data B
DQ
ENA
CLRN
DQ
ENA
CLRN
DQ
ENA
CLRN
Input
Register
Output
Register
Embedded Multiplier Block
Data Out
Note to Figure 12–2:
(1) If necessary, you can send these signals through one register to match the data
signal path.
Input Registers
You can send each multiplier input signal into an input register or directly
into the multiplier in 9- or 18-bit sections depending on the operational
mode of the multiplier. You can send each multiplier input signal through
a register independently of each other (e.g., you can send the multiplier’s
12–4
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007