EP2C5T144I8N Datasheet, PDF (208/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Clocking
Table 7–8. Global Clock Network Connections (Part 3 of 3)
Global Clock
Network Clock
Sources
DPCLK3 (1)
Global Clock Networks
All Cyclone II Devices
EP2C15 through EP2C70 Devices Only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
v
Notes to Table 7–8:
(1) See the Cyclone II Architecture chapter in Volume 1 of the Cyclone II Device Handbook for more information on DPCLK
pins.
(2) This pin only applies to EP2C5 and EP2C8 devices.
(3) These pins only apply to EP2C15 devices and larger. Only one of the two CDPCLK pins can feed the clock control
block. The other pin can be used as a regular I/O pin.
If the dedicated clock pins are not used to feed the global clock networks,
they can be used as general-purpose input pins to feed the logic array
using the MultiTrack interconnect. However, if they are used as
general-purpose input pins, they do not have support for an I/O register
and must use LE-based registers in place of an I/O register.
Clock Control Block
Every global clock network is driven by a clock control block residing
either on the top, bottom, left, or right side of the Cyclone II device. The
global clock network has been optimized for minimum clock skew and
delay.
Table 7–9 lists the sources that can feed the clock control block, which in
turn feeds the global clock networks.
Table 7–9. Clock Control Block Inputs (Part 1 of 2)
Input
Description
Dedicated clock inputs
Dedicated clock input pins can drive clocks or
global signals, such as asynchronous clears,
presets, or clock enables onto a given global
clock network.
Dual-purpose clock (DPCLK and
CDPCLK) I/O inputs
DPCLK and CDPCLK I/O pins are bidirectional
dual function pins that can be used for high fan-
out control signals, such as protocol signals,
TRDY and IRDY signals for PCI, or DQS for
DDR, via the global clock network.
7–24
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007