EP2C5T144I8N Datasheet, PDF (275/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

External Memory Interfaces
DDR Output Registers
Figure 9–14 shows a schematic representation of DDR output
implemented in a Cyclone II device. The DDR output logic is
implemented using LEs in the LAB adjacent to the output pin. Two
registers synchronize two serial data streams. The registered outputs are
then multiplexed by the common clock to drive the DDR output pin at
two times the data rate.
Figure 9–14. DDR Output Implementation for DDR Memory Interfaces
datain_h
LE
Register
data1
Output Register A_{O data0 sel}
DQ
datain_l
LE
Register
-90˚ Shifted clk
Output Register B_O
While the clock signal is logic-high, the output from output register A_O is
driven onto the DDR output pin. While the clock signal is logic-low, the
output from output register B_O is driven onto the DDR output pin. The
DDR output pin can be any available user I/O pin. Altera recommends
the use of altdq and altdqs megafunctions to implement this output
logic. This automatically provides the required tight placement and
routing constraints on the LE registers and the output multiplexer.
Figure 9–15 shows examples of functional waveforms from a DDR output
implementation.
Altera Corporation
February 2007
9–21
Cyclone II Device Handbook, Volume 1