EP2C5T144I8N Datasheet, PDF (395/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Configuring Cyclone II Devices
Figure 13–15. Concurrent PS Configuration of Multiple Devices Using an Enhanced Configuration Device
(1) VCC
VCC (1)
VCC
VCC
Cyclone II Device 1
10 kΩ (3) (3) 10 kΩ
DCLK
DATA0
nSTATUS
CONF_DONE
N.C. nCEO (4) nCONFIG
nCE
MSEL1
MSEL0
GND
N.C.
Cyclone II Device 2
DCLK
DATA0
nSTATUS
CONF_DONE
nCEO (4) nCONFIG
nCE
MSEL1
MSEL0
GND
GND
GND
Enhanced
Configuration
Device
DCLK
DATA0
DATA1
DATA[2..6]
OE (3)
nCS (3)
nINIT_CONF (2)
DATA 7
VCC
Cyclone II Device 8
DCLK
DATA0
nSTATUS
CONF_DONE
N.C. nCEO (4) nCONFIG
nCE
MSEL1
MSEL0
GND
GND
Notes to Table 13–15:
(1) The pull-up resistor should be connected to the same supply voltage as the configuration device.
(2) The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF to nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to V_CC either directly or through a resistor (if reconfiguration is required, a resistor is necessary).
(3) The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
(4) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
The Quartus II software only allows you to set n to 1, 2, 4, or 8. However,
you can use these modes to configure any number of devices from 1 to 8.
For example, if you configure three FPGAs, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the FPGA. For
Altera Corporation
February 2007
13–41
Cyclone II Device Handbook, Volume 1