EP2C5T144I8N Datasheet, PDF (410/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

JTAG Configuration
f
enables the programming software to program or verify the target device.
Configuration data driven into the target device appears on the TDO pin
one clock cycle later.
The Quartus II software verifies successful JTAG configuration upon
completion. At the end of configuration, the software checks the
CONF_DONE pin through the JTAG port. When the Quartus II software
generates a JAM file for a multiple device chain, it contains instructions
so that all the devices in the chain are initialized at the same time. If
CONF_DONE is not high, the Quartus II software indicates that
configuration has failed. If the CONF_DONE pin transitions high, the
software indicates that configuration was successful. After the
configuration bitstream is transmitted serially via the JTAG TDI port, the
TCK port is clocked an additional 299 cycles to perform Cyclone II device
initialization.
The Enable user-supplied start-up clock (CLKUSR) option has no affect
on the device initialization since this option is disabled in the SOF when
configuring the FPGA in JTAG using the Quartus II programmer and
download cable. Therefore, if you turn on the CLKUSR option, you do not
need to provide a clock on CLKUSR when you are configuring the FPGA
with the Quartus II programmer and a download cable.
Cyclone II devices have dedicated JTAG pins that always function as
JTAG pins. You can perform JTAG testing on Cyclone II devices before,
after, and during configuration. Cyclone II devices support the BYPASS,
IDCODE and SAMPLE instructions during configuration without
interruption. All other JTAG instructions may only be issued by first
interrupting configuration and reprogramming I/O pins using the
CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured via the
JTAG port. The CONFIG_IO instruction interrupts configuration. This
instruction allows you to perform board-level testing before configuring
the Cyclone II device or waiting for a configuration device to complete
configuration. If you interrupt configuration, the Cyclone II device must
be reconfigured via JTAG (PULSE_CONFIG instruction) or by pulsing
nCONFIG low after JTAG testing is complete.
For more information, see the MorphIO: An I/O Reconfiguration Solution
for Altera White Paper.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE)
pins on Cyclone II devices do not affect JTAG boundary-scan or
programming operations. Toggling these pins does not affect JTAG
operations (other than the usual boundary-scan operation).
13–56
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007