EP2C5T144I8N Datasheet, PDF (336/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

High-Speed I/O Timing in Cyclone II Devices
Figures 11–14 and 11–15 show differential HSTL class I and II interfaces,
respectively.
Figure 11–14. Differential HSTL Class I Interface
VTT
VTT
Output Buffer
Z0 = 50 Ω
50 Ω
50 Ω
Receiver
Z0 = 50 Ω
Figure 11–15. Differential HSTL Class II Interface
V_TT
V_TT
V_TT
V_TT
Output Buffer
50 Ω
50 Ω
Z0 = 50 Ω
50 Ω
50 Ω
Z0 = 50 Ω
Receiver
High-Speed I/O
Timing in
Cyclone II
Devices
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Cyclone II devices. LVDS, LVPECL,
RSDS, and mini-LVDS I/O standards enable high-speed data
transmission. Timing for these high-speed signals is based on skew
between the data and the clock signals.
High-speed differential data transmission requires timing parameters
provided by integrated circuit (IC) vendors and requires consideration of
board skew, cable skew, and clock jitter. This section provides details on
high-speed I/O standards timing parameters in Cyclone II devices.
11–14
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007