EP2C5T144I8N Datasheet, PDF (213/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
clock sources and the clkena signals for the global clock network
multiplexers can be set through the Quartus II software using the
altclkctrl megafunction.
clkena signals
In Cyclone II devices, the clkena signals are supported at the clock
network level. Figure 7–14 shows how the clkena is implemented. This
allows you to gate off the clock even when a PLL is not being used. Upon
re-enabling the output clock, the PLL does not need a resynchronization
or relock period because the clock is gated off at the clock network level.
Also, the PLL can remain locked independent of the clkena signals since
the loop-related counters are not affected.
Figure 7–14. clkena Implementation
clkena
clkin
DQ
clkena_out
clk_out
Figure 7–15 shows the waveform example for a clock output enable.
clkena is synchronous to the falling edge of the clock (clkin).
This feature is useful for applications that require a low power or sleep
mode. The exact amount of power saved when using this feature is
pending device characterization.
Altera Corporation
February 2007
7–29
Cyclone II Device Handbook, Volume 1