EP2C5T144I8N Datasheet, PDF (211/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

PLLs in Cyclone II Devices
Figure 7–12. Cyclone II Clock Control Blocks Placement
Output from PLL
Clock Control
Block
Input to PLL
4
CLK[8..11]
PLL
3
PLL
3
2
GCLK[8..11]
CLK[0..3]
Clock Control
Block
4
3
Output from PLL
GCLK[0..3]
GCLK[12..15]
GCLK[4..7]
Output from PLL
3
4
Clock Control
Block
CLK[4..7]
PLL
PLL
1
3
4
CLK[12..15]
Clock Control
Block
4
Output from PLL
The inputs to the four clock control blocks on each side are chosen from
among the following clock sources:
■ Four clock input pins
■ Three PLL counter outputs
■ Two DPCLK pins and two CDPCLK pins from both the left and right
sides and four DPCLK pins and two CDPCLK pins from both the top
and bottom
■ Four signals from internal logic
Altera Corporation
February 2007
7–27
Cyclone II Device Handbook, Volume 1