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EP2C5T144I8N Datasheet, PDF (5/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1 | |||
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Contents
Internal Timing ............................................................................................................................... 5â18
Cyclone II Clock Timing Parameters ........................................................................................... 5â23
Clock Network Skew Adders ....................................................................................................... 5â29
IOE Programmable Delay ............................................................................................................. 5â30
Default Capacitive Loading of Different I/O Standards .......................................................... 5â31
I/O Delays ....................................................................................................................................... 5â33
Maximum Input and Output Clock Rate .................................................................................... 5â46
High Speed I/O Timing Specifications ....................................................................................... 5â55
External Memory Interface Specifications .................................................................................. 5â63
JTAG Timing Specifications .......................................................................................................... 5â64
PLL Timing Specifications ............................................................................................................ 5â66
Duty Cycle Distortion ......................................................................................................................... 5â67
DCD Measurement Techniques ................................................................................................... 5â68
Referenced Documents ....................................................................................................................... 5â74
Document Revision History ............................................................................................................... 5â74
Chapter 6. Reference & Ordering Information
Software .................................................................................................................................................. 6â1
Device Pin-Outs ..................................................................................................................................... 6â1
Ordering Information ........................................................................................................................... 6â1
Document Revision History ................................................................................................................. 6â2
Section II. Clock Management
Revision History .................................................................................................................................... 6â1
Chapter 7. PLLs in Cyclone II Devices
Introduction ............................................................................................................................................ 7â1
Cyclone II PLL Hardware Overview .................................................................................................. 7â2
PLL Reference Clock Generation ................................................................................................... 7â6
Clock Feedback Modes ....................................................................................................................... 7â10
Normal Mode .................................................................................................................................. 7â10
Zero Delay Buffer Mode ................................................................................................................ 7â11
No Compensation Mode ............................................................................................................... 7â12
Source-Synchronous Mode ........................................................................................................... 7â13
Hardware Features .............................................................................................................................. 7â14
Clock Multiplication & Division .................................................................................................. 7â14
Programmable Duty Cycle ........................................................................................................... 7â15
Phase-Shifting Implementation .................................................................................................... 7â16
Control Signals ................................................................................................................................ 7â17
Manual Clock Switchover ............................................................................................................. 7â20
Clocking ................................................................................................................................................ 7â21
Global Clock Network ................................................................................................................... 7â21
Clock Control Block ....................................................................................................................... 7â24
Global Clock Network Clock Source Generation ...................................................................... 7â26
Global Clock Network Power Down ........................................................................................... 7â28
Altera Corporation
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Cyclone II Device Handbook, Volume 1
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