EP2C5T144I8N Datasheet, PDF (230/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Memory Modes
Figure 8–4. Cyclone II Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory) ^an
a0
a1
a4
a5
q (synch) doutn-1 doutn
dout0
dout1
dout1
dout1
dout4
q (asynch) doutn
dout0
dout1
dout1
dout1
dout4
dout5
Figure 8–5. Cyclone II Address Clock Enable During Write Cycle Waveform
inclock
wraddress
data
wren
addressstall
latched address
(inside memory)
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
a0
a1
00
01
an
a0
XX
XX
a2
a3
02
03
a1
00
01
02
XX
XX
XX
XX
a4
a5
a6
04
05
06
a4
a5
03
04
05
Memory Modes
Cyclone II M4K memory blocks include input registers that synchronize
writes and output registers to pipeline data, thereby improving system
performance. All M4K memory blocks are fully synchronous, meaning
that you must send all inputs through a register, but you can either send
outputs through a register (pipelined) or bypass the register
(flow-through).
8–8
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2008