EP2C5T144I8N Datasheet, PDF (243/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Cyclone II Memory Blocks
Figure 8–15. Cyclone II Input/Output Clock Mode in Simple Dual-Port Mode
6 LAB Row
Clocks
6
data[ ]
DQ
ENA
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
rdaddress[ ]
DQ
ENA
Read Address
byteena[ ]
DQ
ENA
Data Out
Byte Enable
Notes (1), (2)
DQ
ENA
To MultiTrack
Interconnect (2)
wraddress[ ]
rd_addressstall
wr_addressstall
rden (1)
wren
outclocken
inclocken
inclock
outclock
DQ
ENA
Write Address
Read Address
Clock Enable
Write Address
Clock Enable
DQ
ENA
Read Enable
Write Enable
DQ
ENA
Write
Pulse
Generator
Notes to Figure 8–15:
(1) Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies
to both read and write operations.
(2) See the Cyclone II Device Family Data Sheet in volume 1 of the Cyclone II Device Handbook for more information on the
MultiTrack™ interconnect.
Altera Corporation
February 2008
8–21
Cyclone II Device Handbook, Volume 1