EP2C5T144I8N Datasheet, PDF (377/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

Configuring Cyclone II Devices
Figure 13–9. Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
VCC. (1) VCC. (1)
10 k Ω 10 k Ω
VCC
Cyclone II Device
External Host
(MAX II Device or
Microprocessor)
GND
MSEL0
CONF_DONE
MSEL1
nSTATUS
nCE
GND
DATA0
nCONFIG
DCLK
nCEO N.C. (2)
Notes to Figure 13–9:
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. V_CC should be high
enough to meet the VIH specification of the I/O on the device and the external host.
(2) The nCEO pin can be left unconnected or used as a user I/O pin when it does not feed other device’s nCE pin.
f
Upon power-up, the Cyclone II device goes through a POR, which lasts
approximately 100 ms. During POR, the device resets, holds nSTATUS
low, and tri-states all user I/O pins. Once the FPGA successfully exits
POR, all user I/O pins continue to be tri-stated.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Cyclone II Device Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization.
Reset Stage
While the Cyclone II device’s nCONFIG or nSTATUS pins are low, the
device is in reset. To initiate configuration, the MAX II device must
transition the Cyclone II nCONFIG pin from low to high.
1
V_CCINT and V_CCIO of the banks where the configuration and
JTAG pins reside need to be fully powered to the appropriate
voltage levels in order to begin the configuration process.
When the Cyclone II nCONFIG pin transitions high, the Cyclone II device
comes out of reset and releases the open-drain nSTATUS pin, which is
then pulled high by an external 10-kΩ pull-up resistor. Once nSTATUS is
released, the FPGA is ready to receive configuration data and the MAX II
device can start the configuration at any time.
Altera Corporation
February 2007
13–23
Cyclone II Device Handbook, Volume 1