EP2C5T144I8N Datasheet, PDF (432/470 Pages) Altera Corporation – Cyclone II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Operation Control
Table 14–2 describes the capture and update register capabilities of all
types of boundary-scan cells within Cyclone II devices.
Table 14–2. Cyclone II Device Boundary Scan Cell Descriptions Note (1)
Captures
Drives
Pin Type
User I/O pins
Dedicated clock
input
Dedicated input
(3)
Dedicated
bidirectional
(open drain) (4)
Dedicated
bidirectional (5)
Output
Capture
Register
OUTJ
0
0
0
OUTJ
OE
Input Output
OE
Input
Capture Capture Update Update Update
Register Register Register Register Register
Comments
OEJ PIN_IN PIN_OUT PIN_OE INJ
1
PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
clock network or
logic array
1
PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
control logic
OEJ PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN drives to
configuration
control
OEJ PIN_IN N.C. (2) N.C. (2) N.C. (2) OUTJ drives to
output buffer
Notes to Table 14–2:
(1) TDI, TDO, TMS, TCK, all V_CC and GND pin types do not have BSCs.
(2) N.C.: no connect.
(3) This includes nCONFIG, MSEL0, MSEL1, DATA0, and nCE pins and DCLK (when not used in Active Serial mode).
(4) This includes CONF_DONE and nSTATUS pins.
(5) This includes DCLK (when not used in Active Serial mode).
IEEE Std. 1149.1
BST Operation
Control
Cyclone II devices implement the following IEEE Std. 1149.1 BST
instructions: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE, USERCODE,
CLAMP, and HIGHZ. The BST instruction length is 10 bits. These
instructions are described later in this chapter.
f
For summaries of the BST instructions and their instruction codes, see
the Configuration & Testing chapter in Volume 1 of the Cyclone II Device
Handbook.
The IEEE Std. 1149.1 test access port (TAP) controller, a 16-state state
machine clocked on the rising edge of TCK, uses the TMS pin to control
IEEE Std. 1149.1 operation in the device. Figure 14–5 shows the TAP
controller state machine.
14–6
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007