DS531 Datasheet, PDF (9/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
PLB I/O Signals
Table 3 provides a summary of all Xilinx PLB input/output (I/O) signals, the interfaces under which they are
grouped, and a brief description of the signal.
Table 3: PLB Pin Descriptions
Port
Signal Name
Interface
I/O
Init
State
Description
DCR Signals (Only available in shared bus configuration)
P1 DCR_ABus[0:C_DCR_
AWIDTH-1]
DCR
I
CPU DCR address bus
P2 DCR_Read
DCR
I
CPU read from DCR indicator
P3 DCR_Write
DCR
I
CPU write to DCR indicator
P4 DCR_DBus[0:C_DCR_
DWIDTH-1]
DCR
I
DCR write data bus
P5 PLB_dcrAck
DCR
O
0 PLB DCR data transfer acknowledge
P6 PLB_dcrDBus[0:C_DCR_
DWIDTH-1]
DCR
O
0 PLB DCR read data bus
PLB Status Signals
P7 PLB_rdPendPri[0:1]
Master/Slave O
0 PLB pending read request priority
P8 PLB_wrPendPri[0:1]
Master/Slave O
0 PLB pending write request priority
P9 PLB_rdPendReq
Master/Slave O
0 PLB pending bus read request
indicator
P10 PLB_wrPendReq
Master/Slave O
0 PLB pending bus write request
indicator
P11 PLB_reqPri[0:1]
Master/Slave O
0 PLB current request priority
Master Signals
P12 M_abort[0:C_PLBV46_NUM_
MASTERS-1]
Master
I
Master abort bus request indicator
P13 M_ABus[0:C_PLBV46_NUM_
MASTERS*32-1]
Master
I
Master address bus, lower 32 bits for
each master
P14 M_BE[0:C_PLBV46_NUM_
MASTERS*C_PLBV46_
DWIDTH/8-1]
Master
I
Master byte enables
P15 M_busLock[0:C_PLBV46_NUM_
Master
I
MASTERS-1]
Master bus lock
P16 M_TAttribute[0:16*C_PLBV46_
NUM_MASTERS-1]
Master
I
Master transfer attributes
P17 M_lockErr[0:C_PLBV46_NUM_M Master
I
ASTERS-1]
Master lock error indicator
P18 M_mSize[0:C_PLBV46_NUM_
MASTERS*2 -1]
Master
I
Master data bus port width
P19 M_priority[0:C_PLBV46_NUM_M Master
I
ASTERS*2 -1]
Master bus request priority
DS531 September 21, 2010
www.xilinx.com
9
Product Specification