DS531 Datasheet, PDF (4/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Address Pipelining
The read and write data buses of the PLB can be concurrently active. Therefore, two primary transactions, one read
and one write, are launched sequentially and completed in parallel. Beyond this, the PLB protocol allows for
additional secondary transactions to be acknowledged through the address phase and queued up, waiting to
complete the data transfer when signaled to that the needed data bus is free. The PLB v4.6 protocol allows for such
address pipelining to be arbitrarily deep, but does not require it.
To make use of address pipelining, the Xilinx PLB must incorporate the implied extra state and book-keeping logic
and slaves must be designed to accept secondary transactions. If support is missing in either place, all transactions
proceed as primary transactions and the expense associated with implementing the unused secondary-transaction
capability--whether in the Xilinx PLB or slaves--is wasted.
The Xilinx PLB is introduced into an FPGA embedded computing environment where slaves generally do not
support secondary addresses; however, the MicroBlaze™ processor does support this feature. Therefore, the Xilinx
PLB will support address pipelining by default. However, there is an option to disable address pipelining, when
secondary address support is not needed. The option is disabled by setting C_ADDR_PIPELINING_TYPE=0,
which disables two-deep address pipelining (one primary and one secondary transaction for each of read and
write). Deeper address pipelining is not supported. To get the default of supporting address pipelining, set
C_ADDR_PIPELINING_TYPE=1.
PLB two-deep address pipelining is not limited to the shared bus mode configuration. When the PLB is configured
in a point-to-point topology, the two-deep address pipeline also is enabled. To enable this, both the parameters must
be set as C_P2P=1 and C_ADDR_PIPELINING_TYPE=1. The point-to-point configuration with address pipelining
allows slave devices to assert the Sl_addrAck to the asserted PLB_SAValid, secondary address valid. On read
transactions, the slave must monitor the PLB_rdPrim signal which indicates the primary transaction data phase is
complete and the slave can begin to drive Sl_rdDAck and Sl_rdComp for the secondary transaction which was
previously acknowledged. Figure 3 illustrates this usage case.
X-Ref Target - Figure 3
PLB_Clk
M_Request
M_RNW
PLB_PAValid
PLB_SAValid
PLB_RNW
PLB_rdPrim
PLB_wrPrim
Sl_addrAck
Sl_reArbitrate
Sl_rdComp
Sl_wrComp
1
2
1
2
1
2
DS531_03_061608
Figure 3: Point-to-Point Address Pipelining (AddrAck to SAValid)
DS531 September 21, 2010
www.xilinx.com
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Product Specification