DS531 Datasheet, PDF (13/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 3: PLB Pin Descriptions (Cont’d)
Port
Signal Name
Interface
I/O
Init
State
Description
P84 PLB_SwrDAck
Simulation O
0 Output of slave Sl_wrDAck OR gate
P85 PLB_SwrComp
Simulation O
0 Output of slave Sl_wrComp OR gate
P86 PLB_SwrBTerm
Simulation O
0 Output of slave Sl_wrBTerm OR gate
P87 PLB_SrdDBus[0:C_PLBV46_
DWIDTH-1]
Simulation O
0 Output of slave Sl_rdDBus OR gate
P88 PLB_SrdWdAddr[0:3]
Simulation O
0 Output of slave Sl_rdWdAddr OR
gate
P89 PLB_SrdDAck
Simulation O
0 Output of slave Sl_rdDAck OR gate
P90 PLB_SrdComp
Simulation O
0 Output of slave Sl_rdComp OR gate
P91 PLB_SrdBTerm
Simulation O
0 Output of slave Sl_rdBTerm OR gate
P92 PLB_SMBusy[0:C_PLBV46_
NUM_MASTERS-1]
Simulation O
0 Output of slave Sl_MBusy OR gate
P93 PLB_SMRdErr[0:C_PLBV46_
NUM_MASTERS-1]
Simulation O
0 Output of slave Sl_MRdErr OR gate
P94 PLB_SMWrErr[0:C_PLBV46_
NUM_MASTERS-1]
Simulation O
0 Output of slave Sl_MWrErr OR gate
P95 PLB_Sssize[0:1]
Simulation O
0 Output of slave Sl_SSize OR gate
Upper Address Extension
P97 M_UABus(0:C_PLBV46_NUM_M Master
I
ASTERS*32-1)⁽²⁾
Master upper address bits. (Only the
rightmost C_PLBV46_AWIDTH-32
bits in each 32-bit field are used)
P98 PLB_UABus(0:31)⁽²⁾
Slave
O
Slave upper address bits. (Only the
rightmost C_PLBV46_AWIDTH-32
bits are used)
Notes:
1. The outputs in this section are required to connect with the PLB Monitor Bus Functional Model (BFM) supplied with
the IBM PLB Toolkit. These outputs are not needed otherwise, but can be used as debug signals if desired.
2. UABus ports are required for connection in the EDK tool, but the signal usage is ignored in the core. No address bits
beyond 32-bits are supported at this time.
DS531 September 21, 2010
www.xilinx.com
13
Product Specification