DS531 Datasheet, PDF (31/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Slave Interface[m]
Figure 18 demonstrates all slave[m] interface I/O signals (where m = 0 to C_PLBV46_NUM_ SLAVES-1). See the
IBM 128-Bit Processor Local Bus Architectural Specification (v4.6) for detailed functional descriptions of these signals.
Note that C_PLBV46_NUM_ MASTERS=8, C_PLBV46_DWIDTH=128, and C_PLBV46_AWIDTH=36 in this
diagram.
X-Ref Target - Figure 18
PLB
Core
Clk
SPLB_Rst[m]
PLB_PAValid
PLB_busLock
PLB_MasterID[0:2]
PLB_RNW
PLB_BE[0:15]
PLB_size[0:3]
PLB_type[0:2]
PLB_MSize[0:1]
PLB_TAttribute
SI_MIRQ[m*8:m*8+7]
PLB_LockErr
PLB_abort
M_RNW[n]
PLB_UABus[0:3], PLB_ABus[0:31]
SI_addrAck[m]
SI_wait[m]
SI_SSize[m*2:2+1]
SI_rearbitrate[m]
SI_MBusy[m*8:m8+7]]
SI_MRdErr[m*8:m*8+7, SI_MWrErr[m*8:m*8+7]
PLB_SAValid
PLB_rdPrim[m]
PLB_wrPrim[m]
PLB_wrDBus[0:31]
PLB_wrBurst
SI_wrDAck[m]
SI_wrComp[m]
SI_wrBterm[m]
PLB_rdBurst
SI_rdDBus[m*128:m*128+127]
SI_rdWdAddr[m*4:m*4+3]
SI_RdDAck[m]
SI_rdComp[m]
SI_rdBTerm[m]
Slave[m]
Interface
Figure 18: Slave[n] Interface
DS531_18_051608
DS531 September 21, 2010
www.xilinx.com
31
Product Specification