DS531 Datasheet, PDF (37/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Revision History
The following table shows the revision history for this document.
Date
6/13/08
11/13/08
4/24/09
9/21/10
Version
1.0
1.1
1.2
1.3
Description of Revisions
Initial Xilinx release.
Edited "Address Pipelining" section; converted to current data sheet template.
Replaced references to supported device families and tool name(s) with
hyperlink to PDF file.
Updated the revision number from v1.04a to v1.05a. Updated IP Facts table.
Notice of Disclaimer
Xilinx is providing this design, code, or information (collectively, the “Information”) to you “AS-IS” with no warranty of any
kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free
from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on
the Information. All specifications are subject to change without notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY
WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED
THEREON, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS
IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Except as stated herein, none of the Information may be
copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of
Xilinx.
DS531 September 21, 2010
www.xilinx.com
37
Product Specification