DS531 Datasheet, PDF (29/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Point-to-Point Mode
The PLB v4.6 core can be optimized for point-to-point connections by setting the design parameter, C_P2P = 1. This
configuration allows for optimization when only a single master and single slave device are required to
communicate.
In this mode, components such as the Address Path, Write & Read Data Path Units, and Bus Control Unit are not
included in the core to minimize resource utilization and improve latency. In point-to-point mode, the M_Request
signal can be directly routed to PLB_PAValid with minimal latency. The point-to-point mode still incorporates the
Watchdog Timer to allow PLB_MTimeout to be asserted if the slave device does not respond to PLB_PAValid.
Enabling address pipelining is configurable in point-to-point mode. By setting the design parameter,
C_ADDR_PIPELINING_TYPE = 1, a two-level pipeline is incorporated in the design. In this configuration, an
arbitration state machine controls the assertion of PLB_PAValid and PLB_SAValid.
When the PLB is configured in a point-to-point mode, C_P2P = 1, the bus will ignore any assertion by the master
device on the M_busLock signal. Since only one master is utilizing the bus, there is no need to drive PLB_busLock
and the bus will default this output to ’0’.
DS531 September 21, 2010
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Product Specification