DS531 Datasheet, PDF (32/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
DCR Interface
The device control register (DCR) interface allows the CPU core in the system to read and write the DCRs in the
PLB. The DCR interface is only available in shared bus configuration. For additional information on the DCR bus,
see the IBM 32-Bit Device Control Register Bus Architecture Specifications.
Figure 19 demonstrates all DCR interface input/output signals when C_DCR_DWIDTH = 32 and
C_DCR_AWIDTH=10.
X-Ref Target - Figure 19
PLB_dcrAck
PLB_dcr_DBus[0:31]
PLB
Core
DCR_Read
DCR_Write
DCR_ABus[0:9]
DCR_DBus[0:31]
DCR
Interface
DS531_19_061608
Figure 19: DCR Interface
PLB Operations
The IBM 128-Bit Processor Local Bus Architectural Specification (v4.6) document provides a comprehensive discussion
on the various PLB operations and transfers. The reader is referred to that document for further protocol
description and timing diagrams. Different specific timing relationships can conform to the same protocol and
might reflect different trade-offs between F_MAX, latency and resource usage. Some expected timing characteristics
of a prospective implementation are noted in the following items, without imposing them as rigid requirements.
• M_request to PLB_PAValid delay
• Two cycles when the number of masters is two or more
• One (or possibly 0) cycles when there is one master
• Master-to-slave signals flow combinatorially through a multiplexer whose selection is the active master
• Slave-to-master signals flow combinatorially through an OR concentrator over all slaves, then through a
demultiplexer to the active master
• PLB_rdPrim and PLB_wrPrim react combinatorially to the respective Sl_rdComp or SL_wrComp
DS531 September 21, 2010
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Product Specification