DS531 Datasheet, PDF (24/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
.
X-Ref Target - Figure 12
A : C_PLBV46_DWIDTH=64, C_PLBV46_AWIDTH=32
0
78
31
PLB Byte Enables
B : C_PLBV46_DWIDTH=128, C_PLBV46_AWIDTH=36
0
15
Unused
28
31
PLB Byte Enables
Unused
Figure 12: PEAR_BYTE_EN Register
PLB Addr High
DS531_12_061608
The bit definitions for PEAR_BYTE_EN are shown in Table 10.
Table 10: PLB PEAR_BYTE_EN Bit Definitions
Bit(s)
Name
Core
Access
0 to C_PLBV46_DWIDTH/8-1 Bus Error
Read
Address High _Write(1)
64-C_PLBV46_AWIDTH to 31
Others
Unused, read as zero
Reset
Value
0
Description
Bus Error Byte Enables.
Read: PLB byte enable value when
error occurred
Write: If the Test Enable bit is asserted
in the PACR, this field is
writable.Otherwise, a write has no
effect.
Bus Error Byte Enables, high bits.
Notes:
1. This register can be written if the Test Enable bit is asserted in the PACR. Unused bits are not writable.
PEAR_SIZE_TYPE: PLB Error Size and Type
This register contains the values of the PLB size and type during the transaction that caused the error as shown in
Figure 13. This register is cleared when SYS_Rst is asserted or a 1 is written to the Software Reset bit. The bit
definitions for PEAR_SIZE_TYPE are shown in Table 11.
X-Ref Target - Figure 13
PLB Type
0
34
67
PLB Size
Unused
Figure 13: PEAR_SIZE_TYPE Register
31
DS531_13_061608
DS531 September 21, 2010
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Product Specification