DS531 Datasheet, PDF (33/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Bus Time-Out
Because the time out concept for PLB V4.6 differs from PLB V3.4, it is illustrated here in more detail. Please note that
a time out finishes a transaction in the address phase instead of proceeding, as with V3.4, to a data phase with the
arbiter supplying artificial address and data acknowledges. Figure 20 shows a bus time-out for an attempted
transfer to which no slave responds within the time out interval of 16 clocks. The PLB arbitration logic samples the
Sl_wait, Sl_rearbitrate and M_Abort signals 16 cycles after the initial assertion of the PLB_PAValid signal,
and if all are negated, it asserts the PLB_MTimeout signal. This completes all handshaking for the transfer.
X-Ref Target - Figure 20
Cycles 0
PLB_Clock
M_request[n]
M_RNW[n]
M_BE[n*16.n*16+15]
M_Size[n*4.n*4+3]
M_type[n*3.n*3+2]
M_abort[n]
M_UABus[n*4.N*4+3].M_ABus[n*32.n*32+31]
M_wrBurst[n]
PLB_PAValid
Sl_wait[m]
Sl_rearbitrate[m]
Sl_AddrAck[m]
PLB_MTimeout[n]
12
34
19 20 21 22 23
valid
valid
valid
valid
valid
DS531_20_061608
Figure 20: Bus Time-Out
Time-Out Suppression
If a slave cannot respond within 16 cycles, it can suppress the time out and buy more time. Figure 21 shows a slave
suppressing the time out by responding with Sl_wait[m] within 16 clocks. When the slave is eventually ready, it
responds with Sl_AddrAck[m] (shown) or Sl_rearbitrate[m].
X-Ref Target - Figure 21
Cycles 0 1 2 3 4 5 17 18
PLB_Clock
M_request[n]
M_RNW[n]
valid
M_BE[n*16.n*16+15]
valid
M_Size[n*4.n*4+3]
valid
M_type[n*3.n*3+2]
valid
M_abort[n]
M_UABus[n*4.N*4+3].M_ABus[n*32.n*32+31]
valid
M_wrBurst[n]
PLB_PAValid
Sl_wait[m]
Sl_rearbitrate[m]
Sl_AddrAck[m]
PLB_MTimeout[n]
DS531_21_061608
Figure 21: Time-Out Suppression
DS531 September 21, 2010
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Product Specification