DS531 Datasheet, PDF (10/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 3: PLB Pin Descriptions (Cont’d)
Port
Signal Name
Interface
P20 M_rdBurst[0:C_PLBV46_NUM_
MASTERS-1]
P21 M_request[0:C_PLBV46_NUM_
MASTERS-1]
P22 M_RNW[0:C_PLBV46_NUM_
MASTERS-1]
P23 M_size[0:C_PLBV46_NUM_
MASTERS*4 -1]
P24 M_type[0:C_PLBV46_NUM_
MASTERS*3-1]
P25 M_wrBurst[0:C_PLBV46_
NUM_MASTERS-1]
P26 M_wrDBus[0:C_PLBV46_NUM_
MASTERS*C_PLBV46_
DWIDTH -1]
P27 PLB_MAddrAck[0:C_PLBV46_
NUM_MASTERS-1]
P28 PLB_MBusy[0:C_PLBV46_NUM
_MASTERS-1]
P29 PLB_MRdErr[0:C_PLBV46_
NUM_MASTERS-1]
P30 PLB_MWrErr[0:C_PLBV46_
NUM_MASTERS-1]
P31 PLB_MRdBTerm[0:C_PLBV46_N
UM_MASTERS-1]
P32 PLB_MRdDAck[0:C_PLBV46_
NUM_MASTERS-1]
P33 PLB_MRdDBus[0:C_PLBV46_N
UM_MASTERS*C_PLBV46_
DWIDTH -1]
P34 PLB_MRdWdAddr[0:C_PLBV46_
NUM_MASTERS*4 -1]
P35 PLB_MRearbitrate[0:C_PLBV46_
NUM_MASTERS-1]
P36 PLB_MSSize[0:C_PLBV46_
NUM_MASTERS*2 -1]
P37 PLB_MWrBTerm[0:C_PLBV46_N
UM_MASTERS-1]
P38 PLB_MWrDAck[0:C_PLBV46_
NUM_MASTERS-1]
P39 PLB_MTimeout[0:C_PLBV46_
NUM_MASTERS-1]
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
Master
I/O
Init
State
Description
I
Master burst read transfer indicator
I
Master bus request
I
Master read not write
I
Master transfer size
I
Master transfer type
I
Master burst write transfer indicator
I
Master write data bus
O
0 PLB Master address acknowledge
O
0 PLB Master slave busy indicator
O
0 PLB Master slave read error indicator
O
0 PLB Master slave write error
indicator
O
0 PLB Master terminate read burst
indicator
O
0 PLB Master read data acknowledge
O
0 PLB Master read data bus
O
0 PLB Master read word address
O
0 PLB Master bus re-arbitrate indicator
O
0 PLB Master slave data bus port width
O
0 PLB Master terminate write burst
indicator
O
0 PLB Master write data acknowledge
O
0 PLB address-phase timeout indicator
DS531 September 21, 2010
www.xilinx.com
10
Product Specification