DS531 Datasheet, PDF (18/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 4: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects
P68 Sl_SSize[0:C_PLBV46_NUM_
SLAVES*2-1]
P69 Sl_wait[0:C_PLBV46_NUM_
SLAVES-1]
P70 Sl_wrBTerm[0:C_PLBV46_NUM
_ SLAVES-1]
P71 Sl_wrComp[0:C_PLBV46_NUM
_ SLAVES-1]
P72 Sl_wrDAck[0:C_PLBV46_NUM_
SLAVES-1]
P73 Bus_Error_Det
P74 Sl_MIRQ[0:C_PLBV46_NUM_
SLAVES*C_PLBV46_NUM_
MASTERS-1]
P75 PLB_MIRQ[0:C_PLBV46_NUM
_ MASTERS-1]
P76 PLB_Clk
P77 SYS_Rst
P78 PLB_Rst
P79 SPLB_Rst[0:C_PLBV46_NUM_
SLAVES-1]
P80 MPLB_Rst[0:C_PLBV46_NUM_
MASTERS-1]
P81 PLB_SaddrAck
P82 PLB_Swait
P83 PLB_Srearbitrate
P84 PLB_SwrDAck
P85 PLB_SwrComp
P86 PLB_SwrBTerm
P87 PLB_SrdDBus[0:C_PLBV46_
DWIDTH-1]
P88 PLB_SrdWdAddr[0:3]
P89 PLB_SrdDAck
P90 PLB_SrdComp
P91 PLB_SrdBTerm
P92 PLB_SMBusy[0:C_PLBV46_
NUM_MASTERS-1]
Depends
Relationship Description
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G2
Width varies with the number of PLB slaves.
G5,G10
G1, G2
C_IRQ_ACTIVE determines the active state of the
interrupt. If C_DCR_INTFCE=0, then interrupts are
always enabled, otherwise, interrupts are enabled by
writing to the PLB Control Register.
Width varies with the number of PLB slaves and the
number of PLB masters.
G1
Width varies with the number of PLB masters.
G2
Width varies with the number of PLB slave devices.
G1
Width varies with the number of PLB master devices.
G4
Width varies with the size of the PLB data bus.
G1
Width varies with the number of PLB masters.
DS531 September 21, 2010
www.xilinx.com
18
Product Specification