DS531 Datasheet, PDF (16/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Table 4: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects
P23 M_size[0:C_PLBV46_NUM_
MASTERS*4 -1]
P24 M_type[0:C_PLBV46_NUM_
MASTERS*3-1]
P25 M_wrBurst[0:C_PLBV46_
NUM_MASTERS-1]
P26 M_wrDBus[0:C_PLBV46_NUM
_MASTERS*C_PLBV46_
DWIDTH -1]
P27 PLB_MAddrAck[0:C_PLBV46_
NUM_MASTERS-1]
P28 PLB_MBusy[0:C_PLBV46_NU
M_MASTERS-1]
P29 PLB_MRdErr[0:C_PLBV46_
NUM_MASTERS-1]
P30 PLB_MWrErr[0:C_PLBV46_
NUM_MASTERS-1]
P31 PLB_MRdBTerm[0:C_PLBV46_
NUM_MASTERS-1]
P32 PLB_MRdDAck[0:C_PLBV46_
NUM_MASTERS-1]
P33 PLB_MRdDBus[0:C_PLBV46_
NUM_MASTERS*C_PLBV46_
DWIDTH -1]
P34 PLB_MRdWdAddr[0:C_PLBV46
_NUM_MASTERS*4 -1]
P35 PLB_MRearbitrate[0:C_PLBV46
_NUM_MASTERS-1]
P36 PLB_MSSize[0:C_PLBV46_
NUM_MASTERS*2 -1]
P37 PLB_MWrBTerm[0:C_PLBV46_
NUM_MASTERS-1]
P38 PLB_MWrDAck[0:C_PLBV46_
NUM_MASTERS-1]
P39 PLB_MTimeout[0:C_PLBV46_
NUM_MASTERS-1]
P40 PLB_abort
P41 PLB_ABus[0:31]
P42 PLB_BE[0:C_PLBV46_DWIDT
H/8-1]
P43 PLB_busLock
P44 PLB_TAttribute[0:15]
P45 PLB_lockErr
Depends
Relationship Description
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1, G4 Width varies with the size of the PLB data bus and
the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1, G4 Width varies with the size of the PLB data bus and
the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G1
Width varies with the number of PLB masters.
G3
Width varies with the size of the PLB address bus.
G4
Width varies with the size of the PLB data bus.
DS531 September 21, 2010
www.xilinx.com
16
Product Specification