DS531 Datasheet, PDF (34/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
Design Implementation
Target Technology
The target technology is an FPGA listed in the IP Facts table on page 1.
Device Utilization and Performance Benchmarks
Because the PLB is a module that is used with other design pieces in the FPGA, the utilization and timing numbers
reported in this section are just estimates. As the PLB is combined with other pieces of the FPGA design, the
utilization of FPGA resources and timing of the PLB design will vary from the results reported here.
The PLB benchmarks shown in Table 13 are for a Virtex^®-5 (XC5VFX70T) device.
Table 13: PLB FPGA Performance and Resource Utilization Benchmarks
Parameter Values
Device Resources
Slices
Slice
Slice LUTs
Registers
f_MAX
(MHz)
1
1
1
1
1
1
1
1
0
1
4
0
4
1
0
4
4
0
4
4
0
4
4
0
8
8
0
8
8
0
8
16
0
0
N/A
4
10
1
N/A
11
17
1
0
46
128
1
0
64
131
1
0
242
175
0
0
259
156
1
0
243
179
1
1
278
197
0
0
354
184
1
0
331
221
1
0
438
229
14
35
67
149
559
658
655
683
1214
1185
1296
635.3
500.2
378.7
357.5
220.8
252.5
222.8
227.6
235.8
203.2
228.4
Notes:
1. These benchmark designs contain only the PLB with registered inputs and outputs without any additional
logic. Benchmark numbers approach the performance ceiling rather that representing performance under
typical user conditions.
DS531 September 21, 2010
www.xilinx.com
34
Product Specification