DS531 Datasheet, PDF (3/37 Pages) Xilinx, Inc – Four levels of dynamic master request priority

LogiCORE IP Processor Local Bus (PLB) v4.6 (v1.05a)
X-Ref Target - Figure 2
Cycles 0
SYS_plbClk
Mn_request[n]
M_UAbus.Mn_Abus.Mn_priority.Mn_RNW
Mn_type.Mn_Ssize.Mn_size.M_BE
Mn_Burst.Mn_busLock
Mn_abort
PLB_PAValid
PLB_reqPrio.PLB_RNW
PLB_ABus.PLB_type.PLB_Ssize.PLB_size.PLB_BE
PLN_MnwrBurst.PLB_busLock
PLB_abort
SI_addrAck.SI_wrAck.SI_wrComp
PLB_MnAddrAck.PLB_MnwrDAck
Mn_wrDBus
PLB_wrDBus
1 (A1)
3 (A3)
5
valid
valid
initial value
valid
next value
valid
valid
initial value
valid
next value
initial data
next data
initial data next data
DS531_02_061608
Figure 2: Three-Cycle Arbitration (Xilinx Implementation)
During the bus arbitration cycle (in a fixed priority arbitration scheme), the bus arbitration control unit uses two
priority bits from each requesting master to determine which master is granted the bus. The two bits
M_priority[i*2:i*2+1] are the priority bits for master i. The two priority bits are interpreted as an integer between 0
and 3—with the bit at the lowest index having the highest weight of two. The value of zero represents the lowest
priority. From there, priority increases with increasing numerical value.
In addition, the Xilinx PLB arbitration logic supports the fixed priority scheme to handle “tie” situations (that is,
situations when two or more masters request the bus simultaneously while presenting the same level of request
priority). Selection of the priority mode during tie situations is shown in Table 1 where n =
C_PLBV46_NUM_MASTERS.
Table 1: Priority Order for Bus Masters
Highest Priority
Decreasing Priority
Master ₀
Master ₁ ...
Lowest Priority
Master _n-2 Master _n-1
In the round robin arbitration scheme, the bus arbitration control unit allows the least recently used master to win
arbitration and control the bus. Once a master is granted the bus, it will then become the lowest priority master in
the next arbitration cycle. Configuring the PLB in a round robin scheme allows each master in the system an
opportunity to be granted the bus. This is critical in system configurations where certain masters can lock out other
masters from being granted the bus simply due to connection ordering on the PLB. Round robin arbitration
prevents the need of each master to increase the M_priority bits to the highest level in order for a chance to win
arbitration on the bus.
DS531 September 21, 2010
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